A semiconductor wafer of silicon is manufactured with a layer of an interlayer dielectric, ILD, which can be a dielectric, such as, silica including SiO2 and TEOS, and further, such as, a low K dielectric. The ILD is suitable as base on which multilevel integrated circuits are to be fabricated. Metal filled trenches are fabricated in the ILD, for example, by a damascene process. Metal, such as, copper, in the trenches, and provides circuit interconnects. A thin barrier film, for example, tantalum, meaning elemental tantalum or tantalum alloy including tantalum nitride, between the copper metal and the ILD, provides a barrier to migration of the metal into the ILD. The barrier film covers the surface of the ILD including the trenches. The barrier film and a thin film of the copper metal are deposited in succession, for example, by successive chemical vapor deposition processes, followed by an electroplating process for depositing copper metal to fill the trenches. Copper metal covers the barrier film, and fills the trenches to provide circuit interconnects. The successive layers of the barrier film and copper metal cause the wafer to have a topography of peaks and valleys that require polishing to achieve a polished planar surface that is suitable as a base for integrated circuits. The wafer may comprise a standard test wafer, on which are performed tests for the effectiveness of polishing operations.
The wafer is polished by a polishing system known as CMP, referred to as either or both, chemical-mechanical planarization and chemical-mechanical polishing. The CMP system moves the wafer against a moving polishing pad, and uses a combination of the moving polishing pad with polishing fluids at an interface with the wafer being polished, to remove the metal films by polishing pressure and chemical reaction of the metal films to the polishing fluid. According to accepted practices, a first step polishing operation is performed to remove the copper metal to the level of the underlying barrier film. Thereby, a test wafer is provided, having a top layer of barrier film, and further having trenches in an underlying ILD. The trenches contain metal that provide circuit interconnects. Further, the metal in the trenches are dished as a result of the first step polishing operation. The first step polishing operation is followed by a second step polishing operation that removes the barrier film to the surface of the underlying ILD, and which further results in the ILD being polished with a mirror-like, polished planar surface suitable for subsequent fabrication of integrated circuits. Further, the wafer is left with metal in the trenches to provide circuit interconnects. The metal in the trenches are dished as a result of being subjected to the second step polishing operation.
The CMP polishing system would desirably result in a polished planar wafer surface without residual metal films on the polished surface of the ILD, and with all of the trenches having metal at heights that are even with the level of the polished surface. However, chemical reaction and mechanical friction, applied by the polishing operation results in undesired removal of metal from the trenches, referred to as dishing. Further, the wafer can be subjected to excessive polishing, to ensure complete removal of metal from the ILD surface, which results in erosion of the ILD surface. Excessive polishing can cause undesired rounding of the corner edges of the trenches, altering critical dimensions of the circuit interconnects in the trenches.
A long existing need exists for a CMP system that minimizes, dishing of circuit interconnects in trenches, erosion of an ILD surface and rounding of corner edges of the trenches.